Role: Sr. Analyst-CAE (ASIC Design, Place and Route)
Location: San Jose, California (Onsite)
Type- Fulltime/Contract
Skills: Place and Route (PnR) Expert
ASIC Design (Cadence Genus, Innovus, Tempus, iSpatial)
DFT understanding will be added advantage Should have knowledge
Cadence is Must
Job Description:
We are looking for a Place and Route (PnR) Expert to drive the physical implementation of ASIC blocks, ensuring robust timing closure and adherence to physical constraints. The ideal candidate will have hands-on experience with Cadence Genus, Innovus, Tempus, and iSpatial flows, enabling a seamless transition from synthesis to final layout. This role involves optimizing performance, power, and area (PPA) while ensuring Design Rule Check (DRC) and Layout vs. Schematic (LVS) compliance.
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